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verified SJR 0,112 · Q4 • database Latindex indexed
Journal of Low Power Electronics
United States · American Scientific Publishe...
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Journal of Low Power Electronics

Journal of Low Power Electronics is a journal indexed in SJR in Electrical and Electronic Engineering with an H index of 17. It has an SJR impact factor of 0,112 and it has a best quartile of Q4. It has an SJR impact factor of 0,112.

ISSN: 1546-1998
Publisher: American Scientific Publishers
Category: Electrical and Electronic Engineering
Indexation: verifiedLatindex
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schedule CountryOfPapers database fields
SJR Impact Factor trending_up
0,112 Q4
H-index 17
Acceptance rate pie_chart
43%
Source Acceptance_Rate
Time to publication hourglass_top
NPD
Field NPD
Publication cost (APC) payments
NPD Subscription
Non-OA path NPD

Metrics

Scimago and CountryOfPapers database fields

Latindex

SJR Impact

0,112

H-index

17

Docs (year)

0

Docs 3y

40

Total refs

0

Cites 3y

9

Citable 3y

38

Cites/Doc 2y

0

Ref/Doc

0.0

Immediate OA

—

Embargoed OA

NPD

Non OA / Submission

—

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Best articles by citations

A Scan Controller Concept for Low Power Scan Tests

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WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays

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Asynchronous Parallel Platforms with Balanced Performance and Energy

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Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications

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An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks

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An Ultra-Low Power CMOS Temperature Sensor for Passive RFID Application

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An Effective Combinatorial Algorithm for Gate-Level Threshold Voltage Assignment

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An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

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An Advanced Low Power and Versatile CMOS Current Driver for Multi-Electrode Cochlear Implant Microstimulator

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Addressing Productivity Challenges in Domain-Specific Reconfigurable Platforms: A Case Study on Extended Kalman Filter-Based Motor Control

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Ab-Initio Modeling of Effect of Boron and Phosphorus Doping in CoFe/MgO Magnetic Tunnel Junctions

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A Technology Based Complexity Model for Reversible Cuccaro Ripple-Carry Adder

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A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010

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A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation

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A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs

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A Novel Threshold Voltage Assignment for 3D Multicore Designs

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A Novel Low Power Three-Input OR/XNOR Gate Design

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A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market

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A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design

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A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic

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A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder

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A Four-Transistor Level Converter for Dual-Voltage Low-Power Design

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A Dynamic Power Estimation Method for System on Chip Designs

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A Compact Two Dimensional Analytical Modeling of Nanoscale Fully Depleted Dual Material Gate Strained SOI/SON MOSFETs for Subdued SCEs

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