verified SJR 0,496 · Q2 • database Scopus / SJR & Web of Science indexed

United States · Institute of Electrical and...

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IEEE Computer Architecture Letters

IEEE Computer Architecture Letters is a journal indexed in SJR in Hardware and Architecture with an H index of 42. It has an SJR impact factor of 0,496 and it has a best quartile of Q2. It has an SJR impact factor of 0,496.

ISSN: 1556-6056

Publisher: Institute of Electrical and Electronics Engineers Inc.

Category: Hardware and Architecture

Indexation: verifiedScopus / SJR verifiedWeb of Science

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schedule CountryOfPapers database fields

SJR Impact Factor trending_up

0,496 Q2

H-index 42

Acceptance rate pie_chart

34%

Source Acceptance_Rate

Time to publication hourglass_top

NPD

Field NPD

Publication cost (APC) payments

NPD Subscription

Non-OA path NPD

Metrics

Scimago and CountryOfPapers database fields

Scopus / SJR Web of Science

SJR Impact

0,496

H-index

Docs (year)

Docs 3y

132

Total refs

830

Cites 3y

236

Citable 3y

132

Cites/Doc 2y

1.88

Ref/Doc

12.97

Immediate OA

—

Embargoed OA

NPD

Non OA / Submission

—

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Best articles by citations

Asymmetric Resilience for Accelerator-Rich Systems

Weighted Random Routing on Torus Networks

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling

Covert Channels on GPGPUs

Corollaries to Amdahl's Law for Energy

Constrained Energy Optimizationin Heterogeneous Platforms UsingGeneralized Scaling Models

Cloud Server Benchmark Suite for Evaluating New Hardware Architectures

CIM: A Reliable Metric for Evaluating Program Phase Classifications

Cache Calculus: Modeling Caches through Differential Equations

Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER

Branch Misprediction Prediction: Complementary Branch Predictors

Balanced Instruction Cache: Reducing Conflict Misses of Direct-Mapped Caches through Balanced Subarray Accesses

SHOW MORE ARTICLES

Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs

A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management

An Overview of Static Pipelining

An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation

AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs

Adopting System Call Based Address Translation into User-Level Communication

Accelerator Memory Reuse in the Dark Silicon Era

A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks

A Performance-Energy Model to Evaluate Single Thread Execution Acceleration

A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator

A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip

FAQs

IEEE Computer Architecture Letters has an SJR of 0,496 (best quartile Q2) in the CountryOfPapers database.

Immediate OA APC is not available (NPD).

The acceptance rate recorded for IEEE Computer Architecture Letters is 34%.

IEEE Computer Architecture Letters

Metrics

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Researcher reviews

Best articles by citations

FAQs

What is the SJR of IEEE Computer Architecture Letters?

What is the APC / publication cost?

What is the acceptance rate?