ISSN: 1556-6056

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IEEE Computer Architecture Letters Q2 Unclaimed

Institute of Electrical and Electronics Engineers Inc. United States

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IEEE Computer Architecture Letters is a journal indexed in SJR in Hardware and Architecture with an H index of 42. It has an SJR impact factor of 0,496 and it has a best quartile of Q2. It has an SJR impact factor of 0,496.

Type: Journal

Type of Copyright:

Languages:

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Hardware and Architecture (Q2)

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

0,496

SJR Impact factor

42

H Index

64

Total Docs (Last Year)

132

Total Docs (3 years)

830

Total Refs

236

Total Cites (3 years)

132

Citable Docs (3 years)

1.88

Cites/Doc (2 years)

12.97

Ref/Doc

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Aims and Scope

Best articles by citations

An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation

Foreword

Performance Modeling and Bottleneck Analysis of EDGE Processors Using Dependence Graphs

Editorial: Letter from the Editor-in-Chief

Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC

AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs

Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads

PRR-PRR Dynamic Relocation

MultiAmdahl: How Should I Divide My Heterogenous Chip?

Threads and Data Mapping: Affinity Analysis for Traffic Reduction

Orbital Edge Computing: Machine Inference in Space

Enhancing the L1 Data Cache Design to Mitigate HCI

SHOW MORE ARTICLES

Corollaries to Amdahl's Law for Energy

Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities

A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator

Energy Aware Persistence: Reducing the Energy Overheads of Persistent Memory

Nahalal: Cache Organization for Chip Multiprocessors

Using tag-match comparators for detecting soft errors

A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER

A Case for Hybrid Discrete-Continuous Architectures

HAD-TWL: Hot Address Detection-Based Wear Leveling for Phase-Change Memory Systems with Low Latency

Power Management of Datacenter Workloads Using Per-Core Power Gating

Exploiting Existing Copies in Register File for Soft Error Correction