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verified SJR 0,357 · Q3 • database Scopus / SJR & Web of Science indexed
IEEE Design and Test
United States · IEEE Computer Society
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IEEE Design and Test

IEEE Design and Test is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 87. It has an SJR impact factor of 0,357 and it has a best quartile of Q3. It has an SJR impact factor of 0,357.

ISSN: 2168-2356
Publisher: IEEE Computer Society
Category: Software
Indexation: verifiedScopus / SJR verifiedWeb of Science
open_in_new Portal NPD menu_book Guidelines NPD
schedule CountryOfPapers database fields
SJR Impact Factor trending_up
0,357 Q3
H-index 87
Acceptance rate pie_chart
26% Selective
Source Acceptance_Rate
Time to publication hourglass_top
NPD
Field NPD
Publication cost (APC) payments
NPD Subscription
Non-OA path NPD

Metrics

Scimago and CountryOfPapers database fields

Scopus / SJR Web of Science

SJR Impact

0,357

H-index

87

Docs (year)

85

Docs 3y

262

Total refs

856

Cites 3y

403

Citable 3y

230

Cites/Doc 2y

1.6

Ref/Doc

10.07

Immediate OA

—

Embargoed OA

NPD

Non OA / Submission

—

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Best articles by citations

Sensor Driven Reliability and Wearout Management

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Test Challenges for 3D Integrated Circuits

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The Embedded Object Concept: a Lego-like Approach to Making Embedded Systems

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The Joy of Scheduling

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Time Out of Mind

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Time-Critical Systems Design, Part II

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TTTC News

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Variability and Reliability Awareness in the Age of Dark Silicon

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VPOS: A Specific Operating System for the FPGA Verification of Microprocessor System-level Functions

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The Art of Certifying Analog/Mixed-Signal Circuits

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Speeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC]

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Silicon Nanophotonics

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Statistics in Semiconductor Test, Going Beyond Yield

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Robust On-chip Signaling by Staggered and Twisted Bundle

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Report of the 2015 Embedded Systems Week (ESWEEK)

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Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities

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Parameter-Invariant Design of Medical Alarms

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Parallelizing GPGPU-Sim for Faster Simulation with High Fidelity

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Overview of 3-D Architecture Design Opportunities and Techniques

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Overcoming Early-Life Failure and Aging Challenges for Robust System Design

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Opportunities and Challenges for 3D Systems and Their Design

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Modeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation

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Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis

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Hierarchical Test Integration Methodology for 3-D ICs

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