ISSN: 2168-2356

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IEEE Design and Test Q3 Unclaimed

IEEE Computer Society United States

Unfortunately this journal has not been claimed yet. For this reason, some information may be unavailable.

IEEE Design and Test is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 87. It has an SJR impact factor of 0,357 and it has a best quartile of Q3. It has an SJR impact factor of 0,357.

Type: Journal

Type of Copyright:

Languages:

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Electrical and Electronic Engineering (Q3) Hardware and Architecture (Q3) Software (Q3)

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

0,357

SJR Impact factor

87

H Index

85

Total Docs (Last Year)

262

Total Docs (3 years)

856

Total Refs

403

Total Cites (3 years)

230

Citable Docs (3 years)

1.6

Cites/Doc (2 years)

10.07

Ref/Doc

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Formal Aspects of Computing Q3
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Aims and Scope

Best articles by citations

Parallelizing GPGPU-Sim for Faster Simulation with High Fidelity

A Look at Asynchronous Design and Photonic Network-on-a-Chip (PNoC)

A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller

A Survey of Silicon Photonics for Energy Efficient Manycore Computing

An Overview of Mixed-Signal Production Test from a Measurement Principle Perspective

Statistics in Semiconductor Test, Going Beyond Yield

3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization

TTTC News

Hierarchical Test Integration Methodology for 3-D ICs

Comparative Study of Authenticated Encryption Targeting Lightweight IoT Applications

Balancing new reliability challenges and system performance at the architecture level

Systematic Design of Medical Capsule Robots

SHOW MORE ARTICLES

Event-Triggered Sensing for High-Quality and Low-Power Cardiovascular Monitoring Systems

Report of the 2015 Embedded Systems Week (ESWEEK)

Hardware Obfuscation and Logic Locking: A Tutorial Introduction

Time-Critical Systems Design, Part II

Test Challenges for 3D Integrated Circuits

Modeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation

Robust On-chip Signaling by Staggered and Twisted Bundle

Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems

Time Out of Mind

Challenges and Trends in Modern SoC Design Verification

Speeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC]

Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures