ISSN: 2168-2356
Journal Home
Journal Guideline
IEEE Design and Test Q2 Unclaimed
IEEE Design and Test is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 85. It has an SJR impact factor of 0,489 and it has a best quartile of Q2. It has an SJR impact factor of 0,489.
Type: Journal
Type of Copyright:
Languages:
Open Access Policy:
Type of publications:
Publication frecuency: -
- €
Inmediate OANPD
Embargoed OA- €
Non OAMetrics
0,489
SJR Impact factor85
H Index92
Total Docs (Last Year)261
Total Docs (3 years)1197
Total Refs407
Total Cites (3 years)225
Citable Docs (3 years)1.51
Cites/Doc (2 years)13.01
Ref/DocOther journals with similar parameters
Cognitive Systems Research Q2
IEEE Software Q2
ACM Transactions on Programming Languages and Systems Q2
Peer-to-Peer Networking and Applications Q2
Computer Communication Review Q2
Compare this journals
Aims and Scope
Best articles by citations
Parallelizing GPGPU-Sim for Faster Simulation with High Fidelity
View moreA Look at Asynchronous Design and Photonic Network-on-a-Chip (PNoC)
View moreA 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller
View moreA Survey of Silicon Photonics for Energy Efficient Manycore Computing
View moreAn Overview of Mixed-Signal Production Test from a Measurement Principle Perspective
View moreStatistics in Semiconductor Test, Going Beyond Yield
View more3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization
View moreTTTC News
View moreHierarchical Test Integration Methodology for 3-D ICs
View moreComparative Study of Authenticated Encryption Targeting Lightweight IoT Applications
View moreBalancing new reliability challenges and system performance at
 the architecture level
View moreSystematic Design of Medical Capsule Robots
View moreEvent-Triggered Sensing for High-Quality and Low-Power Cardiovascular Monitoring Systems
View moreReport of the 2015 Embedded Systems Week (ESWEEK)
View moreHardware Obfuscation and Logic Locking: A Tutorial Introduction
View moreTime-Critical Systems Design, Part II
View moreTest Challenges for 3D Integrated Circuits
View moreModeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation
View moreRobust On-chip Signaling by Staggered and Twisted Bundle
View moreDesign of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems
View moreTime Out of Mind
View moreChallenges and Trends in Modern SoC Design Verification
View moreSpeeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC]
View moreCrosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures
View more
Comments