IEEE Design and Test
IEEE Design and Test is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 87. It has an SJR impact factor of 0,357 and it has a best quartile of Q3. It has an SJR impact factor of 0,357.
Metrics
Scimago and CountryOfPapers database fields
SJR Impact
0,357
H-index
87
Docs (year)
85
Docs 3y
262
Total refs
856
Cites 3y
403
Citable 3y
230
Cites/Doc 2y
1.6
Ref/Doc
10.07
Immediate OA
—
Embargoed OA
NPD
Non OA / Submission
—
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Researcher reviews
Best articles by citations
Sensor Driven Reliability and Wearout Management
View moreTest Challenges for 3D Integrated Circuits
View moreThe Embedded Object Concept: a Lego-like Approach to Making Embedded Systems
View moreThe Joy of Scheduling
View moreTime Out of Mind
View moreTime-Critical Systems Design, Part II
View moreTTTC News
View moreVariability and Reliability Awareness in the Age of Dark Silicon
View moreVPOS: A Specific Operating System for the FPGA Verification of Microprocessor System-level Functions
View moreThe Art of Certifying Analog/Mixed-Signal Circuits
View moreSpeeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC]
View moreSilicon Nanophotonics
View moreStatistics in Semiconductor Test, Going Beyond Yield
View moreRobust On-chip Signaling by Staggered and Twisted Bundle
View moreReport of the 2015 Embedded Systems Week (ESWEEK)
View morePhysical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities
View moreParameter-Invariant Design of Medical Alarms
View moreParallelizing GPGPU-Sim for Faster Simulation with High Fidelity
View moreOverview of 3-D Architecture Design Opportunities and Techniques
View moreOvercoming Early-Life Failure and Aging Challenges for Robust System Design
View moreOpportunities and Challenges for 3D Systems and Their Design
View moreModeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation
View moreLayout-Aware Optimized Prebond Silicon Interposer Test Synthesis
View moreHierarchical Test Integration Methodology for 3-D ICs
View more