ISSN: 0018-9200

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IEEE Journal of Solid-State Circuits Q1 Unclaimed

Institute of Electrical and Electronics Engineers Inc. United States

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IEEE Journal of Solid-State Circuits is a journal indexed in SJR in Electrical and Electronic Engineering with an H index of 207. It has an SJR impact factor of 2,913 and it has a best quartile of Q1. It is published in English.

Type: Journal

Type of Copyright:

Languages: English

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Electrical and Electronic Engineering (Q1)

Price

- €

Gold OA

-

Green OA

- €

Non OA

Metrics

2,913

SJR Impact factor

207

H Index

309

Total Docs (Last Year)

875

Total Docs (3 years)

8799

Total Refs

4996

Total Cites (3 years)

831

Citable Docs (3 years)

5,92

Cites/Doc (2 years)

28,48

Ref/Doc

Aims and Scope

Other journals with similar parameters

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IEEE Communications Surveys and Tutorials Q1

Best articles

100-Gb/s Multiplexing and Demultiplexing IC Operations in InP HEMT Technology

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

26-42 GHz SOI CMOS Low Noise Amplifier

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

A "Divide and Conquer" Technique for Implementing Wide Dynamic Range Continuous-Time Filters

A 1-V Micropower Log-Domain Integrator Based on FGMOS Transistors Operating in Weak Inversion

A 1.1 G MAC/s Sub-Word-Parallel Digital Signal Processor for Wireless Communication Applications

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.3-GHz fifth-generation SPARC64 microprocessor

A 1.5-GHz 130-nm Itanium 2 processor with 6-MB on-die L3 cache

A 1.8-V 128-Mb 125-MHz multilevel cell memory with flexible read while write

SHOW MORE ARTICLES

A 13.3-Mb/s 0.35-¬µm CMOS analog turbo decoder IC with a configurable interleaver

A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture

A 2.5 - 10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

A 210-mW Graphics LSI Implementing Full 3-D Pipeline With 264 Mtexels/s Texturing for Mobile Multimedia Applications

A 24-GHz CMOS Front-End

A 250-MHz BiCMOS receiver channel with leading edge timing discriminator for a pulsed time-of-flight laser rangefinder

A 2x load/store pipe for a low-power 1-GHz embedded processor

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

A 32-Mb chain FeRAM with segment/stitch array architecture

A 400-MT/s 6.4-GB/s multiprocessor bus interface

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements

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