Default: IEEE Journal of Solid-State Circuits

ISSN: 0018-9200

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IEEE Journal of Solid-State Circuits Q1 Unclaimed

Institute of Electrical and Electronics Engineers Inc. United States
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IEEE Journal of Solid-State Circuits is a journal indexed in SJR in Electrical and Electronic Engineering with an H index of 215. It has an SJR impact factor of 2,571 and it has a best quartile of Q1. It is published in English. It has an SJR impact factor of 2,571.

IEEE Journal of Solid-State Circuits focuses its scope in these topics and keywords: cmos, dram, digital, integrated, frequency, power, gbs, ghz, bit, mw, ...

Type: Journal

Type of Copyright:

Languages: English

Open Access Policy:

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IEEE Journal of Solid-State Circuits


SJR Impact factor


H Index


Total Docs (Last Year)


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Total Cites (3 years)


Citable Docs (3 years)


Cites/Doc (2 years)



Aims and Scope

cmos, dram, digital, integrated, frequency, power, gbs, ghz, bit, mw, receiver, design, chip, test, clock, analog, lowpower, formulatypeinlinetex, amplifiera, k, monolithic, ns, onchip,

Best articles

100-Gb/s Multiplexing and Demultiplexing IC Operations in InP HEMT Technology

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16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

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26-42 GHz SOI CMOS Low Noise Amplifier

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40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

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512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

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A "Divide and Conquer" Technique for Implementing Wide Dynamic Range Continuous-Time Filters

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A 1-V Micropower Log-Domain Integrator Based on FGMOS Transistors Operating in Weak Inversion

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A 1.1 G MAC/s Sub-Word-Parallel Digital Signal Processor for Wireless Communication Applications

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A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

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A 1.3-GHz fifth-generation SPARC64 microprocessor

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A 1.5-GHz 130-nm Itanium 2 processor with 6-MB on-die L3 cache

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A 1.8-V 128-Mb 125-MHz multilevel cell memory with flexible read while write

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A 13.3-Mb/s 0.35-µm CMOS analog turbo decoder IC with a configurable interleaver

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A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture

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A 2.5 - 10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

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A 210-mW Graphics LSI Implementing Full 3-D Pipeline With 264 Mtexels/s Texturing for Mobile Multimedia Applications

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A 24-GHz CMOS Front-End

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A 250-MHz BiCMOS receiver channel with leading edge timing discriminator for a pulsed time-of-flight laser rangefinder

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A 2x load/store pipe for a low-power 1-GHz embedded processor

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A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

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A 32-Mb chain FeRAM with segment/stitch array architecture

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A 400-MT/s 6.4-GB/s multiprocessor bus interface

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A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

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A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements

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