ISSN: 1549-8328

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IEEE Transactions on Circuits and Systems I: Regular Papers Q1 Unclaimed

Institute of Electrical and Electronics Engineers Inc. United States

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IEEE Transactions on Circuits and Systems I: Regular Papers is a journal indexed in SJR in Electrical and Electronic Engineering with an H index of 163. It has an SJR impact factor of 0,861 and it has a best quartile of Q1. It has an SJR impact factor of 0,861.

IEEE Transactions on Circuits and Systems I: Regular Papers focuses its scope in these topics and keywords: applicationsa, wideband, circuits, power, frequency, current, demodulator, descent, cordic, electrochemical, ...

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Publication frecuency: -

Categories: Electrical and Electronic Engineering (Q1)

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Metrics

IEEE Transactions on Circuits and Systems I: Regular Papers

0,861

SJR Impact factor

163

H Index

481

Total Docs (Last Year)

1062

Total Docs (3 years)

16172

Total Refs

4525

Total Cites (3 years)

1051

Citable Docs (3 years)

4,21

Cites/Doc (2 years)

33,62

Ref/Doc

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Aims and Scope

Best articles by citations

A Deep Investigation of the Synchronization Mechanisms in LC-CMOS Frequency Dividers

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Load Effect Analysis and Maximum Power Transfer Tracking of CPT System

Event-Based Control for Network Systems via Integral Quadratic Constraints

Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture

Frequency-Response Masking-Based Design of Nearly Perfect-Reconstruction Two-Channel FIR Filterbanks With Rational Sampling Factors

Scheduled-Step-Size Affine Projection Algorithm

CMOS-Photonics Codesign of an Integrated DAC-Less PAM-4 Silicon Photonic Transmitter

"Reply to ""Comments on Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers"

A Fast Polar Code List Decoder Architecture Based on Sphere Decoding

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Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification

Distributed LC Resonant Clock Grid Synthesis

Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor

Notes on the State Space Realizations of Rational Order Transfer Functions

Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes

Robust, Low-Complexity, and Energy Efficient Downlink Baseband Receiver Design for MB-OFDM UWB System

Comments on "Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers"

Comments on "Chaotic Characteristics Analysis and Circuit Implementation for a Fractional-Order System"

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Single Underwater Image Restoration Using Adaptive Attenuation-Curve Prior

Systematic Design of Large-Scale Multiport Decoupling Networks

Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs