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IEEE Transactions on Computers Q1 Unclaimed

IEEE Computer Society United States

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IEEE Transactions on Computers is a journal indexed in SJR in Software and Computational Theory and Mathematics with an H index of 141. It has an SJR impact factor of 1,307 and it has a best quartile of Q1. It is published in English. It has an SJR impact factor of 1,307.

IEEE Transactions on Computers focuses its scope in these topics and keywords: digital, performance, memory, simple, algorithms, interconnection, patternsensitive, energyefficient, highspeed, execution, ...

Type: Journal

Type of Copyright:

Languages: English

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Computational Theory and Mathematics (Q1) Hardware and Architecture (Q1) Software (Q1) Theoretical Computer Science (Q1)

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

1,307

SJR Impact factor

141

H Index

295

Total Docs (Last Year)

583

Total Docs (3 years)

10389

Total Refs

2224

Total Cites (3 years)

574

Citable Docs (3 years)

3.7

Cites/Doc (2 years)

35.22

Ref/Doc

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Aims and Scope

Best articles by citations

On the guaranteed throughput of multizone disks

Deriving Petri nets from finite transition systems

Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis

Performance optimization of VoIP calls over wireless links using h.323 protocol

Performance of ip-based services over GPRS

Carry-save representation is shift-unsafe: the problem and its solution

Disk scheduling on multimedia storage servers

An Optimal Algorithm for Determining the Visibility of a Polygon from an Edge

Performance Prediction for Large-Scale Parallel Applications Using Representative Replay

A BDD-based algorithm for analysis of multistate systems with multistate components

Multiaccess memory system for attached simd computer

Multiple-seed tpg structures

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Performance modeling and prediction of nondedicated network computing

Interference-Aware Cooperative Communication in Multi-Radio Multi-Channel Wireless Networks

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An effective pixel rasterization pipeline architecture for 3d rendering processors

Failure-detecting arithmetic convolutional codes and an iterative correcting strategy

Rapid Prototyping and Evaluation of Intelligence Functions of Active Storage Devices

Experiences, strategies, and challenges in building fault-tolerant CORBA systems

Class-based decompressor design for compressed instruction memory in embedded processors

Elliptic-Curve-Based Security Processor for RFID

Coordinated en-route Web caching

New Efficient MDS Array Codes for RAID Part II: Rabin-Like Codes for Tolerating Multiple (greater than or equal to 4) Disk Failures

A mobile agent-based advanced service architecture for wireless internet telephony: design, implementation, and evaluation