verified SJR 1,156 · Q1 • database Scopus / SJR & Web of Science indexed

United States · IEEE Computer Society

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IEEE Transactions on Computers

IEEE Transactions on Computers is a journal indexed in SJR in Software and Computational Theory and Mathematics with an H index of 145. It has an SJR impact factor of 1,156 and it has a best quartile of Q1. It is published in English. It has an SJR impact factor of 1,156.

IEEE Transactions on Computers focuses its scope in these topics and keywords: digital, interconnection, patternsensitive, matrix, performance, simple, systemsa, memory, n, highspeed, ...

ISSN: 0018-9340

Editorial: IEEE Computer Society

Category: Software

Indexation: verifiedScopus / SJR verifiedWeb of Science

Unclaimed profile — some fields may be incomplete.

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SJR Impact Factor trending_up

1,156 Q1

H-index 145

Tasa de Aceptación pie_chart

22% Selectiva

Fuente Acceptance_Rate

Tiempo a publicación hourglass_top

NPD

Campo Sin dato

Coste de Publicación (APC) payments

NPD Subscription

Ruta Non-OA NPD

Metrics

Campos Scimago / CoP — sin series inventadas

Scopus / SJR Web of Science

SJR Impact

1,156

H-index

145

Docs (year)

257

Docs 3y

709

Total refs

10038

Cites 3y

3256

Citable 3y

702

Cites/Doc 2y

4.42

Ref/Doc

39.06

Immediate OA

—

Embargoed OA

NPD

Non OA / Submission

—

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Best articles by citations

Algorithmic mapping of neural network models onto parallel SIMD machines

Zero-aliasing space compaction of test responses using a single periodic output

Composable proxy services to support collaboration on the mobile internet

Combining Crypto with Biometrics Effectively

Class-based decompressor design for compressed instruction memory in embedded processors

Carry-save representation is shift-unsafe: the problem and its solution

Area-time efficient sign detection technique for binary signed-digit number system

Analysis of Reliability Dynamics of SSD RAID

An Optimal Algorithm for Determining the Visibility of a Polygon from an Edge

An efficient multipolling mechanism for IEEE 802.11 wireless LANs

An effective pixel rasterization pipeline architecture for 3d rendering processors

An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories

SHOW MORE ARTICLES

An analysis of cache performance of multimedia applications

"Addendum to ""voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems"

A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays

A new scheme for reducing link and signaling costs in mobile ip

A new approach to fault-tolerant wormhole routing for mesh-connected parallel computers

A mobile agent-based advanced service architecture for wireless internet telephony: design, implementation, and evaluation

A geometric theorem for network design

A Fully-Pipelined Hardware Design for Gaussian Mixture Models

A cost-effective pipelined divider with a small lookup table

A class of code compression schemes for reducing power consumption in embedded microprocessor systems

A BIST pattern generator design for near-perfect fault coverage

A BDD-based algorithm for analysis of multistate systems with multistate components

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