ISSN: 1063-8210
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Q1 Unclaimed
IEEE Transactions on Very Large Scale Integration (VLSI) Systems is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 113. It has an SJR impact factor of 0,94 and it has a best quartile of Q1. It is published in English. It has an SJR impact factor of 0,94.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems focuses its scope in these topics and keywords: cmos, noise, power, active, faults, currentsa, cryptosystemselftimed, design, deskewing, detectability, ...
Type: Journal
Type of Copyright:
Languages: English
Open Access Policy:
Type of publications:
Publication frecuency: -
- €
Inmediate OANPD
Embargoed OA- €
Non OAMetrics
0,94
SJR Impact factor113
H Index179
Total Docs (Last Year)731
Total Docs (3 years)5993
Total Refs2717
Total Cites (3 years)724
Citable Docs (3 years)3.37
Cites/Doc (2 years)33.48
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Aims and Scope
Best articles by citations
Object-oriented domain specific compilers for programming FPGAs
View moreFine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures
View moreLeast-square estimation of average power in digital CMOS circuits
View moreFast floorplanning for effective prediction and construction
View moreEffective Radii of On-Chip Decoupling Capacitors
View moreLocally clocked pipelines and dynamic logic
View moreUnifying mesh- and tree-based programmable interconnect
View moreUsing Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance
View morePower-optimal encoding for a DRAM address bus
View moreVariable Resistance Spectrum Assignment in Phase Change Memory Systems
View moreCPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers
View moreA New Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles
View moreUnifying simulation and execution in a design environment for FPGA systems
View moreDesign of synchronous and asynchronous variable-latency pipelined multipliers
View morePower estimation in adiabatic circuits: a simple and accurate model
View moreAnt colony system application to macrocell overlap removal
View moreImproving path delay testability of sequential circuits
View moreA Robust Random Number Generator Based on a Differential Current-Mode Chaos
View moreEfficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems
View moreEvaluation of energy consumption in RC ladder circuits driven by a ramp input
View moreQuantitative study of the impact of design and synthesis options on processor core performance
View moreBIST-based test and diagnosis of FPGA logic blocks
View moreEmpirical models for net-length probability distribution and applications
View moreDuet: an accurate leakage estimation and optimization tool for dual-V/sub t/ circuits
View more
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