ISSN: 1063-8210

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Q1 Unclaimed

Institute of Electrical and Electronics Engineers Inc. United States

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 119. It has an SJR impact factor of 0,937 and it has a best quartile of Q1. It is published in English. It has an SJR impact factor of 0,937.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems focuses its scope in these topics and keywords: active, faults, power, noise, cmos, detectability, drivers, dynamic, deskewing, analysismanaging, ...

Type: Journal

Type of Copyright:

Languages: English

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Electrical and Electronic Engineering (Q1) Hardware and Architecture (Q2) Software (Q2)

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

0,937

SJR Impact factor

119

H Index

215

Total Docs (Last Year)

628

Total Docs (3 years)

6611

Total Refs

2190

Total Cites (3 years)

624

Citable Docs (3 years)

3.21

Cites/Doc (2 years)

30.75

Ref/Doc

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Aims and Scope

Best articles by citations

Object-oriented domain specific compilers for programming FPGAs

Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures

Least-square estimation of average power in digital CMOS circuits

Fast floorplanning for effective prediction and construction

Effective Radii of On-Chip Decoupling Capacitors

Locally clocked pipelines and dynamic logic

Unifying mesh- and tree-based programmable interconnect

Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance

Power-optimal encoding for a DRAM address bus

Variable Resistance Spectrum Assignment in Phase Change Memory Systems

CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers

A New Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles

SHOW MORE ARTICLES

Unifying simulation and execution in a design environment for FPGA systems

Design of synchronous and asynchronous variable-latency pipelined multipliers

Power estimation in adiabatic circuits: a simple and accurate model

Ant colony system application to macrocell overlap removal

Improving path delay testability of sequential circuits

A Robust Random Number Generator Based on a Differential Current-Mode Chaos

Efficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems

Evaluation of energy consumption in RC ladder circuits driven by a ramp input

Quantitative study of the impact of design and synthesis options on processor core performance

BIST-based test and diagnosis of FPGA logic blocks

Empirical models for net-length probability distribution and applications

Duet: an accurate leakage estimation and optimization tool for dual-V/sub t/ circuits