ISSN: 1751-8601

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IET Computers and Digital Techniques Q3 Unclaimed

John Wiley & Sons Inc. United Kingdom

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IET Computers and Digital Techniques is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 48. It has an SJR impact factor of 0,393 and it has a best quartile of Q3. It has an SJR impact factor of 0,393.

Type: Journal

Type of Copyright:

Languages:

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Electrical and Electronic Engineering (Q3) Hardware and Architecture (Q3) Software (Q3)

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

0,393

SJR Impact factor

48

H Index

16

Total Docs (Last Year)

81

Total Docs (3 years)

565

Total Refs

128

Total Cites (3 years)

80

Citable Docs (3 years)

1.3

Cites/Doc (2 years)

35.31

Ref/Doc

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Aims and Scope

Best articles by citations

Simulation and development environment for mobile 3D graphics architectures

Inexact-aware architecture design for ultra-low power bio-signal analysis

Coarse-grained reconfiguration: dataflow-based power management

Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips

Energy efficient VLSI architecture of real-valued serial pipelined FFT

Processing while routing: a network-on-chip-based parallel system

Efficient residue number system iterative modular multiplication algorithm for fast modular exponentiation

Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulink¬Æ mixed environment

Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor

Modelling and simulation techniques for highly integrated, low-power wireless sensor networks

Combined input test data volume reduction for mixed broadside and skewed-load test sets

SHOW MORE ARTICLES

Towards a configurable SoC MPEG-4 advanced simple profile decoder

Editorial: Advances in electronics systems simulation

Simple true random number generator for any semi-conductor technology

Morphable hundred-core heterogeneous architecture for energy-aware computation

Efficient composition of scenario-based hardware specifications

Low-distance path-based multicast routing algorithm for network-on-chips

Binary LNS-based nai¬®ve Bayes inference engine for spam control: noise analysis and FPGA implementation

Low-power and error protection coding for network-on-chip traffic

An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC

Probabilistic model for nanocell reliability evaluation in presence of transient errors

Fast INC-XOR codec for low-power address buses

Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study