Journal list Promote Sponsor
verified SJR 0,221 · Q3 • database Scopus / SJR & Web of Science indexed
IET Computers and Digital Techniques
United Kingdom · John Wiley and Sons Ltd
workspace_premium Q3 — Software lock Subscription

IET Computers and Digital Techniques

IET Computers and Digital Techniques is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 49. It has an SJR impact factor of 0,221 and it has a best quartile of Q3. It has an SJR impact factor of 0,221.

ISSN: 1751-8601
Publisher: John Wiley and Sons Ltd
Category: Software
Indexation: verifiedScopus / SJR verifiedWeb of Science
open_in_new Portal NPD menu_book Guidelines NPD
schedule CountryOfPapers database fields
SJR Impact Factor trending_up
0,221 Q3
H-index 49
Acceptance rate pie_chart
31%
Source Acceptance_Rate
Time to publication hourglass_top
NPD
Field NPD
Publication cost (APC) payments
NPD Subscription
Non-OA path NPD

Metrics

Scimago and CountryOfPapers database fields

Scopus / SJR Web of Science

SJR Impact

0,221

H-index

49

Docs (year)

7

Docs 3y

63

Total refs

316

Cites 3y

85

Citable 3y

62

Cites/Doc 2y

1.25

Ref/Doc

45.14

Immediate OA

—

Embargoed OA

NPD

Non OA / Submission

—

shield Researcher voice

Name good journals. Call out predatory ones.

Share what peer review, fees, and timelines were really like. Praise fair editors. Flag APC traps, fake metrics, or spam solicitations — with facts from your submission.

Fair & fast peer review Clear APC / no surprise fees Suspected predatory Fake impact claims
rate_review Write an honest review

Researcher reviews

sentiment_dissatisfied No reviews yet — be the first to share an honest experience.
User
* Only to validate authenticity — identity is not shown publicly.

Best articles by citations

Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs

View more

Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study

View more

Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router

View more

Defect avoidance in programmable devices

View more

Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction

View more

Contention resolution on a broadcast-based distributed shared memory multiprocessor

View more

Construction of an adaptive scan network for test time and data volume reduction

View more

Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays

View more

Computer-aided crosstalk minimisation design for system-on-chip

View more

Combined input test data volume reduction for mixed broadside and skewed-load test sets

View more

Coarse-grained reconfiguration: dataflow-based power management

View more

Co-scheduling tasks on multi-core heterogeneous systems: An energy-aware perspective

View more
SHOW MORE ARTICLES

Charge-based testing BIST for embedded memories

View more

A digital system to emulate wireless networks

View more

Binary LNS-based nai¨ve Bayes inference engine for spam control: noise analysis and FPGA implementation

View more

Bandwidth-aware routing algorithms for networks-on-chip platforms

View more

Approach of genetic algorithm for power-aware testing of 3D IC

View more

Application-oriented cache memory configuration for energy efficiency in multi-cores

View more

Application modelling and hardware description for network-on-chip benchmarking

View more

An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC

View more

Amdahl's law in the context of heterogeneous many-core systems -a survey

View more

Algorithmic-level exploration of discrete signal transforms for partitioning to distributed hardware architectures

View more

Algebra of switching networks

View more

Admitting and ejecting flits in wormhole-switched networks on chip

View more

FAQs