IET Computers and Digital Techniques
IET Computers and Digital Techniques is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 49. It has an SJR impact factor of 0,221 and it has a best quartile of Q3. It has an SJR impact factor of 0,221.
Metrics
Scimago and CountryOfPapers database fields
SJR Impact
0,221
H-index
49
Docs (year)
7
Docs 3y
63
Total refs
316
Cites 3y
85
Citable 3y
62
Cites/Doc 2y
1.25
Ref/Doc
45.14
Immediate OA
—
Embargoed OA
NPD
Non OA / Submission
—
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Researcher reviews
Best articles by citations
Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs
View moreYield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study
View moreDesign of simulation and analytical models for a 2D-meshed asymmetric adaptive router
View moreDefect avoidance in programmable devices
View moreDecision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction
View moreContention resolution on a broadcast-based distributed shared memory multiprocessor
View moreConstruction of an adaptive scan network for test time and data volume reduction
View moreConstant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays
View moreComputer-aided crosstalk minimisation design for system-on-chip
View moreCombined input test data volume reduction for mixed broadside and skewed-load test sets
View moreCoarse-grained reconfiguration: dataflow-based power management
View moreCo-scheduling tasks on multi-core heterogeneous systems: An energy-aware perspective
View moreCharge-based testing BIST for embedded memories
View moreA digital system to emulate wireless networks
View moreBinary LNS-based nai¨ve Bayes inference engine for spam control: noise analysis and FPGA implementation
View moreBandwidth-aware routing algorithms for networks-on-chip platforms
View moreApproach of genetic algorithm for power-aware testing of 3D IC
View moreApplication-oriented cache memory configuration for energy efficiency in multi-cores
View moreApplication modelling and hardware description for network-on-chip benchmarking
View moreAn algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC
View moreAmdahl's law in the context of heterogeneous many-core systems -a survey
View moreAlgorithmic-level exploration of discrete signal transforms for partitioning to distributed hardware architectures
View moreAlgebra of switching networks
View moreAdmitting and ejecting flits in wormhole-switched networks on chip
View more