Integration, the VLSI Journal
Integration, the VLSI Journal is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 50. It has an SJR impact factor of 0,462 and it has a best quartile of Q2. It is published in English. It has an SJR impact factor of 0,462.
Metrics
Scimago and CountryOfPapers database fields
SJR Impact
0,462
H-index
50
Docs (year)
137
Docs 3y
355
Total refs
4961
Cites 3y
1153
Citable 3y
354
Cites/Doc 2y
3.09
Ref/Doc
36.21
Immediate OA
—
Embargoed OA
NPD
Non OA / Submission
—
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Researcher reviews
Best articles by citations
A non-iterative gate resizing algorithm for high reduction in power consumption
View moreVLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements
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View moreA timing-driven placement algorithm with the Elmore delay model for row-based VLSIs
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View moreA TCAD system for VLSI implementation of the CVD process using VHDL
View moreA systolic algorithm for block-regularized RLS identification
View moreA SPAD-based random number generator pixel based on the arrival time of photons
View moreA real-time systolic integer multiplier
View moreA PN-based approach to the high-level synthesis of digital systems
View moreA parallel VLSI architecture of Kalman-filter-based algorithms for signal reconstruction
View moreA note on architectures for large-capacity CAMs
View moreA BDD-based verification method for large synthesized circuits
View moreA new modeling technique for mixed-mode simulation of CMOS circuits
View moreA new approach to the multiport memory allocation problem in data path synthesis
View moreA new approach in feature interaction testing
View moreA new approach for the design of linear systolic arrays for computing third-order cumulants
View moreA modified noising algorithm for the graph partitioning problem
View moreA modem in CMOS technology for data communication on the low-voltage power line
View moreA graph theoretic approach to feed-through pin assignment
View moreA dual precision IEEE floating-point multiplier
View moreA dual basis bit-serial systolic multiplier for GF(2 )
View moreA complete testing strategy based on interacting and hierarchical FSMs
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