ISSN: 0167-9260
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Integration, the VLSI Journal Q3 Unclaimed
Integration, the VLSI Journal is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 46. It has an SJR impact factor of 0,3 and it has a best quartile of Q3. It is published in English. It has an SJR impact factor of 0,3.
Type: Journal
Type of Copyright:
Languages: English
Open Access Policy:
Type of publications:
Publication frecuency: -
- €
Inmediate OANPD
Embargoed OA- €
Non OAMetrics
0,3
SJR Impact factor46
H Index154
Total Docs (Last Year)297
Total Docs (3 years)5511
Total Refs691
Total Cites (3 years)296
Citable Docs (3 years)2.55
Cites/Doc (2 years)35.79
Ref/DocOther journals with similar parameters
Formal Aspects of Computing Q3
Journal of Experimental and Theoretical Artificial Intelligence Q3
Journal of Functional Programming Q3
Journal of Intelligent Systems Q3
International Journal of Innovative Computing, Information and Control Q3
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Aims and Scope
Best articles by citations
Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate
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View moreA real-time systolic integer multiplier
View moreFactored spherical subspace tracking
View moreHow good are slicing floorplans?
View moreHigh-speed redundant reciprocal approximation
View moreModelling, analysis and synthesis of asynchronous control circuits using Petri nets
View moreGenerating new benchmark designs using a multi-terminal net model
View moreA BDD-based verification method for large synthesized circuits
View moreA non-iterative gate resizing algorithm for high reduction in power consumption
View moreSystolic algorithms for solving a sparse system of linear equations in circuit simulation
View moreBoolean function representation and spectral characterization using AND/OR graphs
View moreAuthors' reply to "A note on architectures for large-capacity CAMs"
View moreBounds, designs and layouts for multi-terminal FPIC architectures
View moreMirroring: a technique for pipelining semi-systolic and systolic arrays
View moreRoutability-constrained multi-bit flip-flop construction for clock power reduction
View moreJoint channel estimation and data detection under fading on reconfigurable fabric
View moreAssignment and allocation of highly testable data paths under scan optimization
View moreModeling and designing silicon thin-film inductors and transformers using HSPICE for RFIC applications
View moreSerial diagnostic fault simulation for synchronous sequential circuits
View moreCommunication code generation in systems of affine recurrence equations
View moreNew approach to design for reusability of arithmetic cores in systems-on-chip
View moreA new approach for the design of linear systolic arrays for computing third-order cumulants
View moreA modified noising algorithm for the graph partitioning problem
View more
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