Default: Integration, the VLSI Journal

ISSN: 0167-9260

Journal Home

Journal Guideline

Integration, the VLSI Journal Q3 Unclaimed

Elsevier B.V. Netherlands
Unfortunately this journal has not been claimed yet. For this reason, some information may be unavailable.

Integration, the VLSI Journal is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 46. It has an SJR impact factor of 0,3 and it has a best quartile of Q3. It is published in English. It has an SJR impact factor of 0,3.

Type: Journal

Type of Copyright:

Languages: English

Open Access Policy:

Type of publications:

Publication frecuency: -

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

Integration, the VLSI Journal

0,3

SJR Impact factor

46

H Index

154

Total Docs (Last Year)

297

Total Docs (3 years)

5511

Total Refs

691

Total Cites (3 years)

296

Citable Docs (3 years)

2.55

Cites/Doc (2 years)

35.79

Ref/Doc

Comments

No comments ... Be the first to comment!



Best articles by citations

Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate

View more

A graph theoretic approach to feed-through pin assignment

View more

A real-time systolic integer multiplier

View more

Factored spherical subspace tracking

View more

How good are slicing floorplans?

View more

High-speed redundant reciprocal approximation

View more

Modelling, analysis and synthesis of asynchronous control circuits using Petri nets

View more

Generating new benchmark designs using a multi-terminal net model

View more

A BDD-based verification method for large synthesized circuits

View more

A non-iterative gate resizing algorithm for high reduction in power consumption

View more

Systolic algorithms for solving a sparse system of linear equations in circuit simulation

View more

Boolean function representation and spectral characterization using AND/OR graphs

View more
SHOW MORE ARTICLES

Authors' reply to "A note on architectures for large-capacity CAMs"

View more

Bounds, designs and layouts for multi-terminal FPIC architectures

View more

Mirroring: a technique for pipelining semi-systolic and systolic arrays

View more

Routability-constrained multi-bit flip-flop construction for clock power reduction

View more

Joint channel estimation and data detection under fading on reconfigurable fabric

View more

Assignment and allocation of highly testable data paths under scan optimization

View more

Modeling and designing silicon thin-film inductors and transformers using HSPICE for RFIC applications

View more

Serial diagnostic fault simulation for synchronous sequential circuits

View more

Communication code generation in systems of affine recurrence equations

View more

New approach to design for reusability of arithmetic cores in systems-on-chip

View more

A new approach for the design of linear systolic arrays for computing third-order cumulants

View more

A modified noising algorithm for the graph partitioning problem

View more

FAQS