International Journal of Reconfigurable Computing
International Journal of Reconfigurable Computing is a journal indexed in SJR in Hardware and Architecture with an H index of 19. It is an CC BY Journal with a Single blind Peer Review review system, and It has a price of 922,5 €. The scope of the journal is focused on reconfigurable computing, hardware architectures, high performance systems. It has an SJR impact factor of 0,143 and it has a best quartile of Q4. It is published in English. It has an SJR impact factor of 0,143.
Metrics
Scimago and CountryOfPapers database fields
SJR Impact
0,143
H-index
19
Docs (year)
0
Docs 3y
6
Total refs
0
Cites 3y
3
Citable 3y
6
Cites/Doc 2y
1
Ref/Doc
0.0
Immediate OA
922,5 €
Embargoed OA
NPD
Non OA / Submission
- €
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Researcher reviews
Best articles by citations
A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip
View moreUsing Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems
View moreAn FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick
View moreAn FPGA-Based Adaptable 200MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation
View moreAn FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve
View moreAn ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms
View moreAn Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
View moreAn Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images
View moreAn Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography
View moreAdaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration
View moreAC_ICAP: A Flexible High Speed ICAP Controller
View moreAADL Extension to Model Classical FPGA and FPGA Embedded within a SoC
View moreA Vector-Like Reconfigurable Floating-Point Unit for the Logarithm
View moreA Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips
View moreA System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation
View moreA Scalable Unsegmented Multiport Memory for FPGA-Based Systems
View moreA Reconfigurable System Approach to the Direct Kinematics of a 5D.o.fRobotic Manipulator
View moreA New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation
View moreA High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos
View moreA High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback
View moreA Hardware Filesystem Implementation with Multidisk Support
View moreA Genetic Programming Approach to Reconfigure a Morphological Image Processing Architecture
View moreA Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection
View moreA Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
View more