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International Journal of Reconfigurable Computing Q4 Unclaimed

Hindawi Publishing Corporation United States

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International Journal of Reconfigurable Computing is a journal indexed in SJR in Hardware and Architecture with an H index of 19. It is an CC BY Journal with a Single blind Peer Review review system, and It has a price of 922,5 €. The scope of the journal is focused on reconfigurable computing, hardware architectures, high performance systems. It has an SJR impact factor of 0,133 and it has a best quartile of Q4. It is published in English. It has an SJR impact factor of 0,133.

Type: Journal

Type of Copyright: CC BY

Languages: English

Open Access Policy: Open Access

Type of publications:

Publication frecuency: -

Categories: Hardware and Architecture (Q4)

Price

922,5 €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

International Journal of Reconfigurable Computing

0,133

SJR Impact factor

19

H Index

2

Total Docs (Last Year)

7

Total Docs (3 years)

113

Total Refs

1

Total Cites (3 years)

6

Citable Docs (3 years)

0.25

Cites/Doc (2 years)

56.5

Ref/Doc

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International Journal of Embedded Systems Q4
International Journal of High Performance Systems Architecture Q4
Neural Network World Q4
International Journal of Data Warehousing and Mining Q4
Journal of High Speed Networks Q4

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Aims and Scope

Reconfigurable computing Hardware architectures High performance systems

Best articles by citations

Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems

Multiloop Parallelisation Using Unrolling and Fission

On Self-Timed Circuits in Real-Time Systems

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform

Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input

RapidRadio: A Domain-Specific Productivity Enhancing Framework

An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms

A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm

Current Trends on Reconfigurable Computing

SHOW MORE ARTICLES

Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

A Hardware Filesystem Implementation with Multidisk Support

A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

A Genetic Programming Approach to Reconfigure a Morphological Image Processing Architecture

Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

Hardware Accelerated Sequence Alignment with Traceback

Reconfigurable Multiprocessor Systems: A Review

Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption