ISSN: 1544-3566

Journal Home

Journal Guideline

Transactions on Architecture and Code Optimization Q2 Unclaimed

Association for Computing Machinery (ACM) United States

Unfortunately this journal has not been claimed yet. For this reason, some information may be unavailable.

Transactions on Architecture and Code Optimization is a journal indexed in SJR in Software and Information Systems with an H index of 46. It has an SJR impact factor of 0,628 and it has a best quartile of Q2. It has an SJR impact factor of 0,628.

Type: Journal

Type of Copyright:

Languages:

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Hardware and Architecture (Q2) Information Systems (Q2) Software (Q2)

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

Transactions on Architecture and Code Optimization

0,628

SJR Impact factor

46

H Index

51

Total Docs (Last Year)

176

Total Docs (3 years)

2779

Total Refs

376

Total Cites (3 years)

175

Citable Docs (3 years)

1.98

Cites/Doc (2 years)

54.49

Ref/Doc

Comments

No comments ... Be the first to comment!

Publication speed *

Review quality *

Edition and editorial team *

Institutional email or ORCID *

* The email or ORCID field is only to validate the authenticity of the comment, the identity will not be public. .

Other journals with similar parameters

Cognitive Systems Research Q2
IEEE Software Q2
ACM Transactions on Programming Languages and Systems Q2
Peer-to-Peer Networking and Applications Q2
Computer Communication Review Q2

Compare this journals

Aims and Scope

Best articles by citations

Extending Moore's Law via Computationally Error-Tolerant Computing

Maximizing Heterogeneous Processor Performance Under Power Constraints

ReSense

Efficient remote profiling for resource-constrained devices

Applied inference

Performance Optimization of the HPCG Benchmark on the Sunway TaihuLight Supercomputer

Inter-cluster communication in VLIW architectures

List of Distinguished Reviewers ACM TACO 2014

Optimizing Convolutional Neural Networks on the Sunway TaihuLight Supercomputer

Improving Parallelism in Hardware Transactional Memory

Tolerating process variations in large, set-associative caches

Conserving network processor power consumption by exploiting traffic variability

SHOW MORE ARTICLES

Design of the Java HotSpot‚Ñ¢ client compiler for Java 6

A Case for a More Effective, Power-Efficient Turbo Boosting

Implementing Dense Optical Flow Computation on a Heterogeneous FPGA SoC in C

Performance scalability of decoupled software pipelining

Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution

Architecting a reliable CMP switch architecture

OpenStream

GPU Performance vs. Thread-Level Parallelism

An Evaluation of High-Level Mechanistic Core Models

Bit-split string-matching engines for intrusion detection and prevention

Online diagnosis of hard faults in microprocessors

The Power-optimised Software Envelope