ISSN: 1065-514X
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VLSI Design Q4 Unclaimed
VLSI Design is a journal indexed in SJR in Electrical and Electronic Engineering and Hardware and Architecture with an H index of 25. It has a best quartile of Q4. It is published in English.
Type: Journal
Type of Copyright:
Languages: English
Open Access Policy:
Type of publications:
Publication frecuency: -

- €
Inmediate OANPD
Embargoed OA- €
Non OAMetrics
-
SJR Impact factor25
H Index0
Total Docs (Last Year)6
Total Docs (3 years)0
Total Refs5
Total Cites (3 years)6
Citable Docs (3 years)0
Cites/Doc (2 years)0.0
Ref/DocOther journals with similar parameters
IEEJ Transactions on Fundamentals and Materials Q4
Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University Q4
Laser and Optoelectronics Progress Q4
Elektrotechnik und Informationstechnik Q4
IEEJ Transactions on Electronics, Information and Systems Q4
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Aims and Scope
Best articles by citations
A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180nm
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View moreA Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters
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View morePower Efficient Hierarchical Scheduling for DSP Transformations
View moreTiming Analysis and Optimization for DSM IC - Guest Editorial
View moreTestability Synthesis for Jumping Carry Adders
View moreMaximizing Memory Data Reuse for Lower Power Motion Estimation
View moreBasic Algorithms for the Asynchronous Reconfigurable Mesh
View moreCMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization
View morePartial Reset: An Alternative DFT Approach
View moreBuilding Rectangular Floorplans-A Graph
View moreCharge Pump Circuits for Low-voltage Applications
View moreTiming Challenges for Very Deep Sub-Micron (VDSM) IC
View moreBoolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix
View moreOverlapped Subarray Segmentation: An Efficient Test
View moreNetworks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management
View moreAnalysis and Design of Regular Structures for Robust
View moreLow-power Application-specific Parallel Array Multiplier Design for DSP Applications
View moreAccurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation
View moreSpectral Techniques and Decision Diagrams - Guest Editorial
View moreSpectral Testing of Digital Circuits
View moreFrequency Domain Kernel Estimation for 2nd-order Volterra Models Using Random Multi-tone Excitation
View moreOn SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration
View more
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