Default: IEEE Micro

ISSN: 0272-1732

Journal Home

Journal Guideline

IEEE Micro Q2 Unclaimed

IEEE Computer Society United States
Unfortunately this journal has not been claimed yet. For this reason, some information may be unavailable.

IEEE Micro is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 99. It has an SJR impact factor of 0,722 and it has a best quartile of Q2. It is published in English. It has an SJR impact factor of 0,722.

IEEE Micro focuses its scope in these topics and keywords: cache, architecture, highperformance, intel, insertion, mc, microarchitecture, microarchitectureitanium, microarchitecturenearoptimal, microcontrollerfloppy, ...

Type: Journal

Type of Copyright:

Languages: English

Open Access Policy:

Type of publications:

Publication frecuency: -

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

IEEE Micro

0,722

SJR Impact factor

99

H Index

90

Total Docs (Last Year)

261

Total Docs (3 years)

922

Total Refs

725

Total Cites (3 years)

218

Citable Docs (3 years)

2.97

Cites/Doc (2 years)

10.24

Ref/Doc

Comments

No comments ... Be the first to comment!

Aims and Scope


cache, architecture, highperformance, intel, insertion, mc, microarchitecture, microarchitectureitanium, microarchitecturenearoptimal, microcontrollerfloppy, microprocessors, multiprocessors, network, nonuniform, pentium, piezoelectricssetduelingcontrolled, applicationsenergy, processor, processorsthe, adaptive, computing, architecturessynchronous, block, blue, cachingtuning, chess, chipsinside, codenamed, coherence, approaches, core, data, dataflow, disk, emotion, geoscience, grandmaster,



Best articles by citations

Hot chips and soggy software

View more

Windows XP hacks: 100 industrial strength tips and tools [Book Review]

View more

Is there a silicon way to intelligence?

View more

High-Speed Packet Processing using Reconfigurable Computing

View more

The proposed SSBLT standard doubles the VME64 transfer rate

View more

Scaling Reverse Time Migration Performance through Reconfigurable Dataflow Engines

View more

End-to-end performance of 10-gigabit ethernet on commodity systems

View more

The 68040 processor. 2. Memory design and chip

View more

The Hardware Security Behind Azure Sphere

View more

Neurocontrol for lateral vehicle guidance

View more

Conformance testing of VMEbus and Multibus II products

View more

Repetitive stress injuries

View more
SHOW MORE ARTICLES

Pygmalion: ESPRIT II project 2059, neurocomputing

View more

Punch: web portal for running tools

View more

Experimentation with hypercube database engines

View more

Research and development needs for advanced vehicle control systems

View more

Virtual reality in Japan

View more

Figure-ground segregation using an analog VLSI chip

View more

Addressing the challenges of advanced packaging and interconnection

View more

A logical design tool for relational databases

View more

Intelligent cruise control and roadside information

View more

RST cache memory design for a highly coupled multiprocessor system

View more

Rapid prototyping using field-programmable logic devices

View more

HASE DLX simulation model

View more

FAQS