ISSN: 0278-0070

Journal Home

Journal Guideline

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Q1 Unclaimed

Institute of Electrical and Electronics Engineers Inc. United States

Unfortunately this journal has not been claimed yet. For this reason, some information may be unavailable.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 132. It has an SJR impact factor of 0,957 and it has a best quartile of Q1. It is published in English. It has an SJR impact factor of 0,957.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems focuses its scope in these topics and keywords: circuit, algorithm, trees, based, style, hardware, placement, optimal, test, approach, ...

Type: Journal

Type of Copyright:

Languages: English

Open Access Policy:

Type of publications:

Publication frecuency: -

Categories: Computer Graphics and Computer-Aided Design (Q1) Electrical and Electronic Engineering (Q1) Software (Q2)

Price

- €

Inmediate OA

NPD

Embargoed OA

- €

Non OA

Metrics

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

0,957

SJR Impact factor

132

H Index

482

Total Docs (Last Year)

1095

Total Docs (3 years)

16309

Total Refs

3358

Total Cites (3 years)

1093

Citable Docs (3 years)

2.8

Cites/Doc (2 years)

33.84

Ref/Doc

Comments

No comments ... Be the first to comment!

Publication speed *

Review quality *

Edition and editorial team *

Institutional email or ORCID *

* The email or ORCID field is only to validate the authenticity of the comment, the identity will not be public. .

Other journals with similar parameters

International Journal of Computer Vision Q1
IEEE Transactions on Pattern Analysis and Machine Intelligence Q1
Information Fusion Q1
IEEE Transactions on Cybernetics Q1
IEEE Transactions on Evolutionary Computation Q1

Compare this journals

Aims and Scope

Best articles by citations

On-chip interconnect modeling by wire duplication

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions

Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting

Transient sensitivity computation in controlled explicit piecewise linear simulation

Identification of Error-Capturing Scan Cells in Scan-BIST With Applications to System-on-Chip

Estimation of signal transition activity in FIR filters implemented by a MAC architecture

Optimizing Designs Using the Additionof Deflection Operations

Global optimization for digital MOS circuits performance

Extraction of Two-Node Bridges From Large Industrial Circuits

ESDInspector: A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism

Constrained Test Generation for Embedded Synchronous Sequential Circuits With Serial-Input Access

An application-level synthesis methodology for multidimensional embedded processing systems

SHOW MORE ARTICLES

A discretization scheme that allows coarse grid-spacing in finite-difference process simulation

Improved integral formulations for fast 3-D method-of-moments solvers

A Hardware Generator for SORN Arithmetic

Simultaneous Driver Sizing and Buffer Insertion Usinga Delay Penalty Estimation Technique

GLFSR-a new test pattern generator for built-in-self-test

Sibling-substitution-based BDD minimization using don't cares

Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells

Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

A Polynomial Time-Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem

An interconnect energy model considering coupling effects

A fast technique based on perfectly matched layers for the full-wave solution of 2-d dispersive microstrip lines