ISSN: 0278-0070
Journal Home
Journal Guideline
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Q2 Unclaimed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems is a journal indexed in SJR in Software and Electrical and Electronic Engineering with an H index of 119. It has an SJR impact factor of 0,556 and it has a best quartile of Q2. It is published in English. It has an SJR impact factor of 0,556.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems focuses its scope in these topics and keywords: circuit, algorithm, trees, based, style, hardware, placement, optimal, test, approach, ...
Type: Journal
Type of Copyright:
Languages: English
Open Access Policy:
Type of publications:
Publication frecuency: -


- €
Inmediate OANPD
Embargoed OA- €
Non OAMetrics
0,556
SJR Impact factor119
H Index536
Total Docs (Last Year)633
Total Docs (3 years)15952
Total Refs2324
Total Cites (3 years)622
Citable Docs (3 years)3,87
Cites/Doc (2 years)29,76
Ref/DocOther journals with similar parameters
Soft Computing Q2
Constraints Q2
Journal of Information Security and Applications Q2
Empirical Software Engineering Q2
Information and Software Technology Q2
Compare this journals
Aims and Scope
Best articles by citations
On-chip interconnect modeling by wire duplication
View moreOSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions
View moreConcurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting
View moreTransient sensitivity computation in controlled explicit piecewise linear simulation
View moreIdentification of Error-Capturing Scan Cells in Scan-BIST With Applications to System-on-Chip
View moreEstimation of signal transition activity in FIR filters implemented by a MAC architecture
View moreOptimizing Designs Using the Additionof Deflection Operations
View moreGlobal optimization for digital MOS circuits performance
View moreExtraction of Two-Node Bridges From Large Industrial Circuits
View moreESDInspector: A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism
View moreConstrained Test Generation for Embedded Synchronous Sequential Circuits With Serial-Input Access
View moreAn application-level synthesis methodology for multidimensional embedded processing systems
View moreA discretization scheme that allows coarse grid-spacing in finite-difference process simulation
View moreImproved integral formulations for fast 3-D method-of-moments solvers
View moreA Hardware Generator for SORN Arithmetic
View moreSimultaneous Driver Sizing and Buffer Insertion Usinga Delay Penalty Estimation Technique
View moreGLFSR-a new test pattern generator for built-in-self-test
View moreSibling-substitution-based BDD minimization using don't cares
View moreDetailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells
View moreNetwork Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems
View moreA Design-Time Method for Building Cost-Effective Run-Time Power Monitoring
View moreA Polynomial Time-Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
View moreAn interconnect energy model considering coupling effects
View moreA fast technique based on perfectly matched layers for the full-wave solution of 2-d dispersive microstrip lines
View more
Comments